Abstract: Systems and methods for asynchronous communication are disclosed. For example, a method for asynchronous communication includes encoding, by a transmitter circuit and according to a first clock signal, a bit sequence by converting a one-bit in the bit sequence into a first sequence and a zero-bit in the bit sequence into a second sequence. A length of the first sequence and a length of the second sequence differ by at least three bits. The method also includes communicating, by the transmitter circuit, the first sequence and the second sequence to a receiver circuit that decodes the first sequence and the second sequence according to a second clock signal that is independent of the first clock signal.

Abstract: A clock recovery device (10), including: a signal conversion circuit (20) that sequentially converts two consecutive symbols of a 2n+1 value (n is a natural number) pulse amplitude modulation signal to one symbol of an NRZ (Non Return to Zero) signal; and a clock recovery circuit (30) that generates a recovery clock signal from the NRZ signal converted by the signal conversion circuit. The signal conversion circuit converts the two consecutive symbols: to 0, when a second symbol is n?1 or less; to 1, when the second symbol is n+1 or more; to 0, when a first symbol is n?1 or less and the second symbol is n; to 1, when a first symbol is n+1 or more and the second symbol is n; to a conversion result of previous two symbols, when both of the two consecutive symbols are n.

Abstract: It is desirable to provide a technology capable of supporting reverse connection in which the front and back of a connector are reversed while expansion of circuit scale is suppressed. A reception control device is provided including a polarity detection unit that detects, as a polarity determination result signal, at least one of a polarity of a first reception signal received by a first reception unit or a polarity of a polarity inversion result of a second reception signal received by a second reception unit and a reception control unit that controls output destinations of a third reception signal received after the first reception signal by the first reception unit and a fourth reception signal received after the second reception signal by the second reception unit, on the basis of the polarity determination result signal.

Abstract: A method for encoding and compressing a bit stream is provided. The method includes: receiving a bit stream; determining whether a first number of bits that are consecutive and identical in the bit stream is greater than or equal to a first preset value; and when the first number is greater than or equal to the first preset value, the first number of bits are encoded as a first code in a first encoding way, wherein the first code is composed of a first prefix and a first suffix, and the first prefix represents what the consecutive bits are and the first suffix represents the first number.

Abstract: A device for transmitting a signal over a serial link includes a transmission processor to carry out, before transmission over the serial link, a scrambling process on successive initial packets of the signal to form a scrambled packet for each initial packet. The transmission processor includes an encoding circuit to carry out an encoding process on each initial packet to deliver an encoded packet. The encoding process includes, for each current initial packet starting from the second, encoding of the current initial packet with the preceding scrambled packet. Calculation circuitry determines, for each initial packet, a bit disparity of the encoded packet and determination of a cumulative bit disparity. Comparison circuitry carries out a comparison process involving the bit disparity of the encoded packet and the cumulative disparity, with the scrambled packet being the encoded packet or the inverted encoded packet, depending on the result of the comparison process.

Abstract: A method of receiving a signal by a receiver in a mobile communication system is provided. The method includes: receiving a reference signal from a transmitter; determining first channel information based on the received reference signal; receiving a data signal based on the first channel information; and determining second channel information based on the received data signal and the first channel information. Iterative channel estimation is performed to reduce channel estimation errors by determining errors of signals received from a turbo decoding unit and using symbol information as pilots even in subcarriers where the pilot signals are not transmitted, and to increase the accuracy of LLR calculation through an iteration process such as a detection and decoding process in comparison with the conventional technology, thereby increasing the reception performance of the turbo decoding unit and improving communication efficiency.

Abstract: An apparatus includes a transmitter adapted to transmit encoded information to a communication link. The transmitter includes a DC balance skew generator. The DC balance skew generator is adapted to skew a DC balance of the information before information is provided to the communication link.

Abstract: Methods and systems for encoding a frame utilizing at least two line-codes having different minimal Hamming distances. The method includes maintaining over the frame absolute value of running disparity lower than or equal to K, while: encoding a first part of the frame utilizing a first line-code having a binary code word length N? and a minimal Hamming distance D?; and encoding a second part of the frame utilizing a second line-code having a binary code word length N? and a minimal Hamming distance D? lower than D?. Where the value of K is lower than both N?/2 and N?/2.

Abstract: Provided are a data receiver circuit and a method of adaptively controlling an equalization coefficient using the same. The data receiver circuit includes n sampling receivers, n decision feedback equalizer (DFE) circuits, and a data recovery circuit. The n sampling receivers are configured to sample an input signal and output n respective sampling signals in response to n respective clock signals. The n DFE circuits are configured to equalize the n respective sampling signals in response to a DFE control signal and generate n respective pre-recovery signals in response to the n equalized sampling signals and n respective previous pre-recovery signals, the DFE control signal for changing an equalization ability of the n DFE circuits. The data recovery circuit is configured to select one of the n respective pre-recovery signals, and output the selected n pre-recovery signal as a recovered input signal.

Abstract: Systems and methods for decoding pulse-width modulated (PWM) data are disclosed. An example decoder filters a data input signal with a one-sided pulse filter. The one-sided pulse filter suppresses short pulses on the data input signal and passes long pulses. The example decoder latch the filtered data signal at the end of each bit time of the data input signal. The duration of pulses that are suppressed by the one-sided pulse filter can be calibrated to compensate for circuit variations and to allow the decoder to operate at various data rates. The decoder can be implemented in a small integrated circuit area and can be power efficient.

Abstract: Digital information is communicated between stacked integrated circuit devices by inductive coupling between arrays of inductors formed from integrated circuit wiring layers. This can be done using a combination of push-pull drivers, common inductor return legs, and balanced sparse ternary encoding. Embodiments result in low power utilization and high pin efficiency.

Abstract: Systems, methods and apparatus for transferring data at a high rate. Examples may provide transmitters and receivers that transfer data at a high rate by encoding the data to be transmitted such that the circuits of the transmitter and receiver operate in their high-gain states. The encoded signal may have an average value that is independent of the data that is conveyed by the transmitted signal. In other examples, the encoding may shape the data signal into a data signal having a high-pass characteristic. When the high-pass encoded signal is transmitted through a channel having a low-pass transfer function, the resulting output signal may have much lower ISI compared to a un-encoded input signal. Transmit and receive circuits, such as amplifiers, laser, and photo-diodes, are biased to operate in their high-gain regions when receiving the encoded data in order to provide high-bandwidth and shorter transition times.

Abstract: A channel sounding method in a wireless local area network (WLAN) system is provided. The method, performed by a transmitter, includes transmitting a null data packet announcement (NDPA) frame to a receiver to initiate a channel sounding procedure; transmitting a null data packet (NDP) to the receiver and receiving a feedback frame. The feedback frame includes a plurality of segment frames and a channel feedback report. The channel feedback report is split into a plurality of feedback segments. Each of the plurality of feedback segments is respectively included in each of the plurality of segment frames. The each of the plurality of segment frames includes a first-segment subfield indicating whether the each of the plurality of feedback segment included is a first segment and a remaining-segment subfield indicating the number of remaining feedback segments.

Abstract: Methods and apparatus intelligently switching between line coding schemes based on context. In one exemplary embodiment, an High Definition Multimedia Interface (HDMI) system is configured to transmit control and video data according to an 8B/10B line coding protocol, and data island data according to TERC4 (TMDS (Transition Minimized Differential Signaling) Error Reduction Coding 4-bit). Various elements of the disclosed HDMI devices are configured to determine when a context switch occurs, and thereafter seamlessly transition between the appropriate line code protocol.

Abstract: An apparatus of transmitting a long training field includes: a station number determination unit configured to determine at least one station to be transmitted using transmission data or channel status information; a transmission stream allocation unit configured to determine the number of transmission streams for each of the least one station determined by the station number determination unit; a long training field number calculation unit configured to calculate the number of long training fields required for each of the at least one station determined by the transmission stream allocation unit and determines the least common multiple of the number of calculated long training fields of each station; and a long training field allocation unit configured to allocate the long training fields for each station to subcarriers allocated to each station to correspond to the least common multiple of the determined long training fields.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: A method and system for beamforming communication in high throughput wireless communications. Analog beamforming involves constructing analog beamforming coefficients for beamforming communication on a wireless channel. Constructing analog beamforming coefficients includes selecting a signal tap from a multi-tap wireless channel for beamforming communication, wherein the selected signal tap has a higher signal quality relative to other signals taps, and determining beamforming coefficients for the selected tap by iterative acquisition of the coefficients based on power iteration.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: An encoding apparatus that converts input digital data and an input clock into three-bit six-state transition encode outputs and outputs them is disclosed. The encoding apparatus has a first state transition control section, second state transition control section, and an output selection section. The first state transition control section changes a state of first data at a positive edge of the input clock. The second state transition control section changes a state of second data at a negative edge of the input clock. The output selection section alternately selects the state of the first state transition control section and the second state transition control section.

Abstract: The present invention aims to provide a transmission device that, in a communication system using multilevel modulation with 2?n levels (n being an integer greater than or equal to two), limits the run length to a predetermined value or less and guarantees DC balance. The transmission device, which transmits data to which 2?n amplitude modulation has been applied, separates data for transmission into n data sequences; encodes one of the n data sequences to guarantee run length, thereby generating a converted data sequence; generates an intermediate data sequence by either inverting or not inverting a specific data sequence so that, based on candidate data, the next output voltage guarantees DC balance; and applies 2?n amplitude modulation to n-bit symbols each of which has a bit in the intermediate data sequence as a most significant bit and bits in the remaining data sequences, excluding the specific data sequence, as subsequent bits.

Abstract: A communication system including a transmitter, a receiver, and a TMDS-like link, in which video data and auxiliary data (typically including timing data associated with other auxiliary data) are transmitted from the transmitter to the receiver, or in which video data are transmitted over the link from the transmitter to the receiver, and auxiliary data (typically including timing data associated with other auxiliary data) are transmitted from the receiver to the transmitter. In typical embodiments the auxiliary data include one or more streams of audio data.

Abstract: A data receiver is provided which includes a front end interface circuit having an alternating current (AC) transmission receiving mode and a direct current (DC) transmission receiving mode. The front end interface circuit includes an offset compensation circuit operable to compensate a DC voltage offset between a pair of differential signals input to the data receiver. The front end interface circuit further includes an AC/DC selection unit operable to switch between (a) the DC transmission receiving mode, and (b) the AC transmission receiving mode, such that the data receiver is operable in (i) the DC transmission mode in which the offset compensation circuit is disabled, (ii) the DC transmission mode in which the offset compensation circuit is enabled, (iii) the AC transmission mode in which the offset compensation circuit is disabled, and (iv) the AC transmission receiving mode in which the offset compensation circuit is enabled.

Abstract: A DC-balanced signal is imposed on the input of a transmission line. Prior to imposing the DC-balanced signal, the input of the transmission line is held at an intermediate DC level that intermediate between the maximum and minimum DC levels of the DC-balanced signal. Alternatively, a compensating pulse is additionally imposed on the input of the transmission line. The compensating pulse compensates for a change in the DC level at the output of the transmission line caused by the imposing of the DC-balanced signal on the input of the transmission line.

Abstract: A radio frequency (RF) transmitter includes a digital radio processor and a baseband processor. A complex analog-to-digital converter (ADC) within the radio processor provides an analog interface to the baseband processor to receive an analog complex modulated baseband signal and convert the analog complex modulated baseband signal to a digital complex modulated baseband signal. A demodulator within the radio processor demodulates the digital complex modulated baseband signal to recreate the original transmit digital data as a demodulated digital signal. The demodulated digital signal is processed by a digital processor in the radio processor to mitigate the effects of various imperfections in the radio processor circuitry.

Abstract: In the case of a method and a device for transmitting data units by way of a transmission medium that comprises at least three adjacent transmission lines, first of all a plurality of codes is supplied. Each code has a number of code sections that corresponds to the number of transmission lines of the transmission medium. Each code section has on an associated transmission line a predetermined signal value, the sum of the signal values for each transmitted code being substantially constant. For each data unit to be transmitted, a code is selected from the plurality of codes, and the selected code is supplied for transmission by way of the transmission medium. The data units and the codes to be transmitted can be supplied in accordance with a predetermined clock pulse, a new code being selected at each new clock pulse, based on the preceding code and the new data unit.

Abstract: In one aspect, the present invention is a system and technique that provides for the systematic development or implementation of codes that increase the robustness of systems employing, for example, PAM-n transmission techniques. The system and technique of this aspect of the invention eliminate, minimize, reduce or limit transitions between extreme signaling levels. As a result, the slew rate employed and/or required by the transmitter may reduce crosstalk and intersymbol interference, and provide for wider “eye” openings from the perspective of the receiver.

Abstract: A method and system for sounding packet exchange in wireless communication involves generating a training request (TRQ) specifying a number of long training fields (LTFs), and transmitting a TRQ from an initiator (transmit station) having multiple antennas to a responder (receive station) over a wireless channel, wherein the TRQ specifies the number of LTFs based on the number of initiator antennas. The responder then transmits a sounding packet to the initiator, wherein the sounding packet includes multiple LTFs corresponding to the number of LTFs specified in the TRQ. Based on the sounding packet, the initiator transmits a beamforming transmission to the responder to enable wireless data communication therebetween.

Abstract: An electronic communications network technology, referred to as 100BASE-TD, offers full duplex operation and robust performance on marginal CAT5 wiring. It highly leverages 100BASE-TX functional blocks and is very complementary to 100BASE-TX, for example with regard to such 100BASE-TX features as auto-negotiation. In particular, the invention provides a carrierless IDLE that requires very low power during ambient operation.

Abstract: Binary information is subjected to RZ encoding and multi-level encoding, and the encoded signal is optically modulated.

Abstract: To transmit information with the aid of a transmit signal exhibiting a number of frequency-specific subcarriers from a first unit to a second unit via a transmission medium, the frequency-selective transmission characteristics of the transmission medium are determined in the first unit and then the subcarriers of the transmit signal are adapted to the transmission characteristics determined. All subcarriers of the transmit signal can be advantageously modulated with the same number of modulation levels as a result of which maximum utilization of the transmission resources of the transmission medium is achieved.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: Methods, software, circuits, architectures, and systems for encoding, decoding and error checking/correcting information, particularly pulse amplitude modulated information. The present invention enjoys particular advantage when used to encode x-unit sequence values of N-ary information into y-unit sequence values of M-ary information and to decode y-unit sequence values of M-ary information into x-unit sequence values of N-ary information, where Nx<My (and particularly where Nx<My, but Nx>My?M). The present invention advantageously provides a straight-forward mechanism for coding information that enables one to take advantage of coding overhead (e.g., unused states in the encoded, transmitted sequence) to accomplish other coding objectives, such as conforming to coding constraints, reducing transmission errors (or increasing the likelihood of successfully correcting such errors), dc balancing the coded information, and under certain conditions, even reducing power consumption.

Abstract: An adapter configured to automatically detect and compensate for differential signal inversion is herein disclosed. In one embodiment, the adapter is part of a computer network having differential conductor pairs conveying differential signals between network devices. The network devices include adapters coupled to transmit and receive signals via the differential conductor pairs. The adapter preferably includes a lane receiver, a decoder, and a synchronization circuit. The lane receiver is configured to receive a single differential signal and to convert the differential signal into a sequence of code symbols. The decoder decodes the code symbols to produce a sequence of received symbols. The synchronization circuit examines the sequence of received symbols to determine if it is incorrect due to inversion of the differential signal, and if so, it causes the lane receiver to correct for the differential signal inversion.

Abstract: In a method for the unidirectional and interference-safe transmission of digital data via radio waves, wherein the data which are composed of data packets each comprising a defined number of bytes and of at least one synchronization packet are transmitted from a transmitter to a receiver, it is proceeded such that each byte is transmitted in a manner comprised of flag bits as start bits, information-representing information bits and identification bits encoding the number of the respective byte and carrying the parity information and that the flag bits and the information bits are inverted in every second byte.

Abstract: A coding device for coding binary data with a particular transmit signal spectrum, the coding device having a data stream separating device for separating a data stream, which consists of the binary data to be coded, into data blocks having a predetermined data block length, a calculating device for calculating the difference between the number of binary data having a second binary state, for each data block, and a transmitting device for transmitting each data block as transformed data block or as non-transformed data block via a communication channel connected to the transmitting device, in such a manner that the total sequence of the data blocks transmitted by the transmitting device on the communication channel exhibits the particular transmit signal spectrum.

Abstract: A method for encoding data bits into channel bits used for recording digital data onto a recording medium or for transmitting digital data via a transmission system. Channel bits “00X”, “010” and “10X” are allotted to 3 patterns of data bits among 4 patterns of data bits having 2 bits, where X designates an indefinite bit which becomes “1” when the channel bit succeeding the indefinite bit is “0” and becomes “0” when the channel bit succeeding the indefinite bit is “1”. Channel bits “000010”, “00000X”, “100010” and “10000X” are allotted to 4 patterns of data bits having 4 bits which are a combination of two bits having a remaining one pattern among the 4 patterns of the data bits having 2 bits and additional two bits.

Abstract: In a method for encoding payload bits for transmission over communications link, data and control information are assembled into n-bit data words, where n is an even number and words for control information are constrained to have zero disparity (equal numbers of binary zero and one digits). The n-bit data words are then encoded into n+2-bit code words by adding a two-bit label; for words carrying control information the label has a value of 10. For other data words the disparity is evaluated; if it is zero, the label bits are 01; if the disparity is non-zero and opposite in sense to the running digital sum of the code words transmitted already, the label bits are 11; otherwise, the data word is inverted, and the label bits are 00.

Abstract: The present invention relates to an optical communications system performance monitoring technique which provides for detecting bit disparity within a data stream. The average power value for a data stream is ascertained by passing the data stream through a low pass filter. The data stream's average power value is then compared with a bit stream baseline power value for a one bit stream and a zero bit stream, the resulting deviation comprising a bit disparity value. An embodiment of this invention would incorporate the use of threshold alarms set for unacceptably high levels of bit disparity. The triggering of these threshold alarms could initiate the transmission of automated customer warnings such as a notification that performance cannot be guaranteed due to high bit disparity on the signal.

Abstract: A bit disparity monitor is disclosed in which a data stream is sub-sampled and logical 1's are detected in the sub-sampled stream. Within a predetermined period, the number of logical 1's is counted and the ratio of logical 1's to the number of bits is determined and compared to acceptable thresholds of bit disparity. In a second embodiment, the data stream is inverted and both the original data stream and the inverted data stream are sampled. The number of logical 1's detected in the sub-sampled original data stream and the number of logical 0's in the sub-sampled inverted data stream are correlated and mismatches, indicative of a transitional sample, are discarded before the bit disparity ratio is determined. Methods of comparing the bit disparity of a data stream to an acceptable threshold are also disclosed.

Abstract: A highly efficient bit encoder and a method related thereto are provided. The bit encoder transmit DC-balanced digital signals over a transmission line. To provide a DC-balanced signal, an input word's single-word disparity (SWD) value is compared to a running word disparity (RWD) value retrieved from a memory register. The RWD value indicates the cumulative DC-imbalance on the transmission line. If the disparity relationship of the SWD and the RWD satisfy a set of predefined rules, the input word is inverted to thereby offset the RWD. An inversion bit is appended to the digital input word to provide an output digital word to indicate to a receiver whether the transmitted output word is inverted to thereby permit recovery of the original system word. In one application, the DC-balanced signal transmits alternately control words and data words.

Abstract: In the case of transmitting upon converting the 8-bit word string data showing signal information to the 10-bit word string data consisting of word synchronous data, 8-bit word string data showing signal information is obtained and after inserting 2 each of the 8-bit word synchronous data and the 8-bit auxiliary word data to be converted to the 10-bit neutral word data, 8 to 10 bits conversion is conducted to the 10-bit word string data and transmitted; when converting the 8-bit word synchronous data to 10-bit word synchronous data, if the immediately preceding word data is the data having plus running disparity, it is converted to 10-bit word synchronous data having minus running disparity, and if the immediately preceding word data is the data having minus running disparity, it is converted to the 10-bit word synchronous data having plus running disparity. Thereby, in the case of reproducing the signal information at the receiving end, the necessary signal synchronization can be certainly obtained.

Abstract: Differential signaling between integrated circuit chips uses fewer than 2 external wires per bit transmitted. Rather than pairing wires into groups of two, the external wires are part of a larger group of 2i+2 wires. Half of the wires in the group are driven low while the other half of the wires are driven high. Since the wires are not paired, adjacent wires can have the same logical state. Differential comparators in the receiver chip compare each wire with all other wires in the group. All outputs of comparators that have a wire as one of its two inputs are input to a majority logic block that evaluates the logical state of the wire. Since half of the wires are in one state, the majority of the remaining wires are in the opposite state of the wire being evaluated. Thus the majority of the comparator outputs indicate the opposite state of the wire being evaluated.

Abstract: A sometimes positive and sometimes negative frequency deviation is associated to a given logic value. The deviation is positive during a certain period of time and then negative, the respective periods being determined so that the cumulated sums of the positive and negative deviation periods are practically equal. A device comprises to this effect an analyzer element for analyzing the asynchronous NRZ signal, having an analog integrator (1, 2) for measuring time, which actuates a switch (3) for selecting a control voltage (MOD) from three voltages. This analyzer element comprises a D-flipflop (2) to whose clock input (CP) is fed the asynchronous NRZ signal, with a resistance-capacitance feedback (4, 1) between its output Q and its input D, and with means (3) for connecting the output {overscore (Q)} of the flipflop (2) to its input D when the NRZ signal has a given logic level.

Abstract: The four tables P, Q, R and S contained in an ROM 2 for 16-24 modulation have a total number of data in which the continuing bits are 2 bits, that is not larger than i bits among the 24 bits, so that the number of continuing bits having the same code is from 2 to 8 bits, so as to have the same characteristics as the (1, 7) code, and to stably lock the PLL. A comparator/selector circuit 5 selects an optimum table out of the tables P, Q, R and S.

Abstract: In the case of transmitting upon converting the 8-bit word string data showing signal information to the 10-bit word string data consisting of word synchronous data, 8-bit word string data showing signal information is obtained and after inserting 2 each of the 8-bit word synchronous data and the 8-bit auxiliary word data to be converted to the 10-bit neutral word data, 8 to 10 bits conversion is conducted to the 10-bit word string data and transmitted; when converting the 8-bit word synchronous data to 10-bit word synchronous data, if the immediately preceding word data is the data having plus running disparity, it is converted to 10-bit word synchronous data having minus running disparity, and if the immediately preceding word data is the data having minus running disparity, it is converted to the 10-bit word synchronous data having plus running disparity. Thereby, in the case of reproducing the signal information at the receiving end, the necessary signal synchronization can be certainly obtained.

Abstract: An encoding circuit with a function of zero continuous-suppression in a data transmission system according to the present invention includes an EXZ detecting unit, a NRZ pulse generating unit and an output control unit. The EXZ detecting unit receives serial data indicating a NRZ signal and binary information indicating a code rule, and outputs EXZ pulses and delay data. The NRZ pulse generating unit receives the EXZ pulses from the EXZ detecting unit, and outputs an EXZ detecting signal, bipolar rule pulses and violation pulses. The output control unit receives the EXZ detecting signal, the bipolar rule pulses and the violation pulses, these are output from the NRZ pulse generating unit, and the delay data from the EXZ detecting unit, and outputs P-pole pulses and N-pole pulses to an external stage, and an odd signal to the NRZ pulse generating unit.

Abstract: A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical `1` signals in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity.

Abstract: The present invention provides a lossless coding scheme that maps unconstrained binary sequences into sequences that obey the (d,k)-RLL constraint while offering a degree of DC control. In the preferred embodiment, the channel encoder is a state machine which uses a single "overlapping" table for all states rather than using multiple tables. Recognizing that a subset of codewords in a first state x.sub.i are identical to a subset of codewords in the second state x.sub.j, the overlapping encoding table uses identical addresses for the subset of identical codewords in the first and second state. Thus addresses for more than one state may point to a single codeword. A number of input bytes can be encoded into two different codewords which have different parity of ones, thus allowing for DC control. Decoding is carried out in a state-independent manner.

Abstract: A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity.

Abstract: Method and apparatus for encoding digital information to be recorded on a magnetic medium is disclosed. The invention provides for receiving a sequence of (2.sup.m n+d) user bits, mapping the sequence of user bits to 2.sup.m dc-free codewords, and recording the 2.sup.m dc-free codewords on a magnetic medium. A modulation coder, which includes a memory containing multiple non-intersecting subconstellations of dc-free codewords, performs the mapping in a non-equiprobable manner such that a particular codeword from a larger subconstellation is more likely to be used than a particular codeword from a smaller constellation. Less desirable codewords, such as those containing relatively long strings of bits having the same value, are assigned to the smaller subconstellations, thereby lessening the likelihood of loss of timing and gain parameters in the system, as well as maximizing the transmission rate and efficient use of the set of possible dc-free sequences of a given length.