Clean Surfaces Patents (Class 148/DIG17)
  • Patent number: 5925574
    Abstract: A method of producing a bipolar transistor composed of collector, base and emitter regions disposed sequentially on a semiconductor substrate. According to the method, a semiconductor layer is deposited on the collector region, the semiconductor layer is cleaned to expose an active surface, an impurity source gas is applied to the exposed active surface while heating the substrate to form an impurity adsorption layer, the impurity is diffused into the semiconductor layer to form the base region, another semiconductor layer is deposited on the base region, this semiconductor layer is cleaned to expose an active surface, another impurity source gas is applied to the exposed active surface while heating the substrate to form another impurity adsorption layer, and impurity is diffused into the semiconductor layer to from the impurity adsorption layer to form the emitter region.
    Type: Grant
    Filed: April 10, 1992
    Date of Patent: July 20, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Kenji Aoki, Tadao Akamine, Yoshikazu Kojima
  • Patent number: 5643633
    Abstract: A tungsten silicide film is deposited from WF.sub.6 and SiCl.sub.2 H.sub.2 onto a substrate so that the tungsten to silicon ratio is substantially uniform through the thickness of the WSi.sub.x film, and the WSi.sub.x film is substantially free of fluorine. The film can be deposited by a multi-stage process where the pressure in the chamber is varied, or by a high temperature, high pressure deposition process in a plasma cleaned deposition chamber. Preferably the SiCl.sub.2 H.sub.2 and the WF.sub.6 are mixed upstream of the deposition chamber. A seeding gas can be added to the process gases.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 1, 1997
    Assignee: Applied Materials, Inc.
    Inventors: Susan G. Telford, Meng Chu Tseng, Michio Aruga, Moshe Eizenberg
  • Patent number: 5637512
    Abstract: There is Disclosed a semiconductor device comprising a silicon film formed on a substrate having at least a surface formed of an insulative material, the silicon film being heat-treated at a temperature below 600.degree. C. and being partially coated with a silicon oxide film formed by electronic cyclotron resonance plasma CVD.
    Type: Grant
    Filed: May 2, 1995
    Date of Patent: June 10, 1997
    Assignee: Seiko Epson Corporation
    Inventors: Mitsutoshi Miyasaka, Thomas W. Little
  • Patent number: 5607878
    Abstract: An inter-level insulation film is formed on a first-level interconnection layer and part of the inter-level insulation film which lies on the first-level interconnection layer is etched to form a contact hole. After a natural oxidation film formed on the surface of part of the first-level interconnection layer which is exposed in the contact hole is removed, the resultant structure is exposed to a gas atmosphere containing halogen to purify the surface of the inter-level insulation film. After this, a contact plug is deposited and formed on the first-level interconnection layer which is exposed in the contact hole by the selective CVD method to fill in the contact hole. A second-level interconnection layer is formed on the inter-level insulation film and the first-level and second-level interconnection layers are electrically connected to each other via the contact plug.
    Type: Grant
    Filed: September 12, 1995
    Date of Patent: March 4, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mari Otsuka, Tomonori Kitakura, Kenichi Otsuka, Kazuya Mori
  • Patent number: 5605867
    Abstract: In a method of manufacturing an insulating film of a semiconductor device by a chemical vapor deposition, a surface of a semiconductor wafer is treated with an organic compound such as ethanol and methanol, and then the semiconductor wafer is transported into a reaction chamber and an insulating film is deposited on the thus treated surface of the semiconductor wafer by a chemical vapor deposition using a raw material such as organic silicon compound. By treating the surface of the semiconductor wafer with the organic compound prior to the deposition, the filling capability and planarization of the insulating film are improved. Further the insulating film thus formed is free from voids and clacks, and an amount of water contained in the insulating film is very small. The treatment of the surface of the semiconductor wafer can be performed simply by spin coating, spaying, vapor exposing or dipping, so that the throughput can be improved.
    Type: Grant
    Filed: March 15, 1993
    Date of Patent: February 25, 1997
    Assignee: Kawasaki Steel Corporation
    Inventors: Nobuyoshi Sato, Tomohiro Ohta, Tadashi Nakano, Hiroshi Yamamoto
  • Patent number: 5563100
    Abstract: A fabrication method of a semiconductor device in which a refractory metal silicide film with a low sheet-resistance can be produced. First, a substructure made of Si-contained material is prepared, the surface of which is covered with a native SiO.sub.2 film. The substructure is typically a single-crystal Si substrate or a polysilicon film. Next, the native SiO.sub.3 film is reduced to be removed from the substructure in a hydrogen atmosphere whose pressure is from 1.times.10.sup.-6 to 1.times.10.sup.3 Torr. Then, a refractory metal film is formed on the surface of the substructure without exposing the substructure to the atmospheric pressure. The refractory metal film is in contact with the uncovered surface of the substructure. The refractory metal film is subjected to a heat-treatment process to react with the substructure, so that a refractory metal silicide film of a first phase is formed at the interface of the refractory metal film and the substructure.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: October 8, 1996
    Assignee: NEC Corporation
    Inventor: Yoshihisa Matsubara
  • Patent number: 5500393
    Abstract: The characteristics of a Schottky junction between diamond and metal causes the diode using the Schottky junction to have a large leakage reverse current and n-value far bigger than 1. A surface of diamond on which a Schottky junction shall be formed is pretreated by oxygen plasma or halogen plasma. The oxygen plasma or hydrogen plasma improves the surface state of the diamond by decoupling the surface C--C bonds and endowing the resulting extra bonds with hydrogen atoms, normalizing the superlattice structure at the surface. Pretreatment of the diamond by the oxygen or halogen plasma improves the diode properties; decreasing reverse current, increasing forward current and decreasing the n-value nearer to 1.
    Type: Grant
    Filed: January 21, 1994
    Date of Patent: March 19, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiki Nishibayashi, Hiromu Shiomi, Naoji Fujimori
  • Patent number: 5492860
    Abstract: A method of growing a layer of a III-V compound semiconductor on a silicon substrate comprises an oxide layer removing step of removing an oxide layer on a surface of the silicon substrate at a first temperature, a low-temperature grown layer forming step of forming a low-temperature grown layer of the III-V compound semiconductor on the silicon substrate while introducing a source gas for Group III and a source gas for Group V at a second temperature lower than the first temperature, and a single crystal layer growing step of growing a single crystal layer of the Group III-V compound semiconductor on the low-temperature grown layer while introducing the source gas for Group III and the source gas for Group V at a third temperature higher than the second temperature and lower than the first temperature.
    Type: Grant
    Filed: April 16, 1993
    Date of Patent: February 20, 1996
    Assignee: Fujitsu Limited
    Inventors: Satoshi Ohkubo, Shinji Miyagaki
  • Patent number: 5492854
    Abstract: A method of manufacturing a semiconductor device includes the step of forming a capacitor. The step includes the step of forming a lower electrode constituted by a polysilicon film which selectively covers a surface of a predetermined insulating film on a semiconductor substrate, and the step of performing heating in an atmosphere containing an SiH.sub.4 gas and removal of a native oxide film on a surface of the lower electrode, and then performing formation of a silicon nitride film without being exposed to an oxygen atmosphere.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: February 20, 1996
    Assignee: NEC Corporation
    Inventor: Koichi Ando
  • Patent number: 5489553
    Abstract: An improved method of gap filling in the dielectric layer using an HF surface treatment is described. Semiconductor device structures are provided in and on a semiconductor substrate wherein the top surfaces of the semiconductor device structures are planarized. A conducting layer is deposited overlying the planarized surface of the semiconductor substrate and patterned. A first oxide layer is conformally deposited over the surfaces of the patterned conducting layer wherein a gap remains between portions of the first oxide layer covering the patterned conducting layer. The surface of the first oxide layer is treated with HF vapor whereby SiOF molecules are formed on the surface of the first oxide layer. A second oxide layer is deposited over the first oxide layer wherein the presence of the SiOF molecules improves the step coverage of the second oxide layer so that the gap is filled by the second oxide layer.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: February 6, 1996
    Assignee: Industrial Technology Research Institute
    Inventor: Lai-Juh Chen
  • Patent number: 5484748
    Abstract: The single crystal silicon wafers which have undergone a treatment with a chemical liquid such as an acid or an alkali are stored without entailing contamination of their surfaces by causing the wafers to be immediately immersed, either directly or after being washed with water, in an aqueous hydrogen peroxide solution. The prevention of the contamination of surfaces of the wafers is attained effectively by setting the concentration of hydrogen peroxide in the aqueous hydrogen peroxide solution in the range of from 0.01 to 30% by weight and the temperature of the aqueous hydrogen peroxide solution at the time that the wafers are immersed in the solution in the range of from 10.degree. to 30.degree. C.
    Type: Grant
    Filed: February 23, 1995
    Date of Patent: January 16, 1996
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kuniyoshi Suzuki, Toshiaki Takaku
  • Patent number: 5455198
    Abstract: A method for fabricating a contact plug capable of achieving a smooth tungsten growth by implanting silicon ions in the bottom surface of a via contact hole not only to remove a polymer formed on the bottom surface of the via contact hole, but also to provide a seed layer for the tungsten growth, and capable of preventing an adverse effect on the contact resistance resulting from a formation of AlF.sub.3 due to a direct contact between Al and WF.sub.6.
    Type: Grant
    Filed: December 27, 1993
    Date of Patent: October 3, 1995
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Kyeong K. Choi
  • Patent number: 5445999
    Abstract: The present invention teaches a method for fabricating an ultrathin uniform dielectric layer over a silicon or polysilicon semiconductor substrate. The method entails first providing a substrate having a conductive area into a chamber. Subsequently, the first conductive material is destabilized by introducing it to reactive gas and radiant energy in situ. The reactive gas can be Ar-H.sub.2, H.sub.2, GeH.sub.4 or NF.sub.3 gas. The radiant energy source can be ultraviolet ("UV") or Tungsten Halogen lamps preferably having an approximate range of 0.2 to 1.6 .mu.m to provide heat of approximately 850.degree. to 1150.degree. C. for approximately 10 to 60 seconds at a vacuum pressure range of 10.sup.-10 Torr to atmospheric pressure. This process removes the native oxide and breaks the molecular clusters present on the silicon or polysilicon surface. Thereafter, a first dielectric layer having a substantially uniform thickness forms directly above the substrate by the in situ introduction of NH.sub.
    Type: Grant
    Filed: November 13, 1992
    Date of Patent: August 29, 1995
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, Viju K. Mathews
  • Patent number: 5413954
    Abstract: A novel vapor phase Si cleaning process comprises simultaneous exposure of the Si surface to a flux of neutral atomic hydrogen and to a flux of ionized particles. The former flux is substantially derived from a plasma, typically a microwave plasma, that is spaced apart from a second plasma, typically a RF plasma, from which the ionized particles are derived. The novel method can be implemented at relatively low cost and facilitates adjustment of the ratio between the two fluxes to result in optimal removal of, e.g., native oxide from the surface.
    Type: Grant
    Filed: November 10, 1992
    Date of Patent: May 9, 1995
    Assignee: AT&T Bell Laboratories
    Inventors: Eray S. Aydil, Richard A. Gottscho, Zhen-Hong Zhou
  • Patent number: 5409544
    Abstract: A method of controlling the adhesion of fine particles to an object in a solution characterized in that the adhesion of fine particles in the solution is prevented or reduced by adding into the solution a material, which is capable of controlling the zeta potential (surface potential) of the fine particles, in the amount of 10.sup.-7 to 25% by volume.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: April 25, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Katsuhiro Ota, Akio Saito, Yoichi Takahara, Hitoshi Oka
  • Patent number: 5387545
    Abstract: An impurity diffusion method which can control a surface atomic concentration from a low to a high surface atomic concentration with a good uniformity is provided. Natural oxide is removed from the surface of a semiconductor substrate with a deoxidizing atmosphere gas as a diffusion atmosphere gas in advance, and then an impurity gas is passed thereto, while passing the deoxidizing atmosphere gas thereto, thereby conducting the diffusion. Flow rate or concentration of impurity of the impurity gas is so set that the impurity atomic concentration of the diffusion layer can be controlled by the flow rate or the concentration of impurity of the impurity gas. The impurity atomic concentration of the diffusion layer can be controlled by adjusting the flow rate or concentration of impurity of the impurity gas, and a diffusion layer having a low impurity atomic concentration can be formed. A shallow junction having a depth of not more than 50 nm can be formed.
    Type: Grant
    Filed: December 12, 1991
    Date of Patent: February 7, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Yukihiro Kiyota, Tohru Nakamura, Takahiro Onai, Taroh Inada
  • Patent number: 5382544
    Abstract: A semiconductor device is manufactured using the electron beam exposure method. A resist is applied on an interlayer dielectric film through a thin metal film, and a contact hole is formed in the interlayer dielectric film. The thin metal film is utilized as a part of a second metal wiring pattern after removing its surface oxides.
    Type: Grant
    Filed: May 25, 1993
    Date of Patent: January 17, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Michikazu Matsumoto, Kazuhiko Hashimoto
  • Patent number: 5372953
    Abstract: As an element of an integrated circuit, an npn bipolar transistor is manufactured as usual in a transistor area covered on a semeconductor substrate with a portion of a field oxide layer by forming openings through the layer portion and forming a highly n-doped collector lead, a highly p-doped base contact region, and then a highly n-doped emitter region. A field oxide film unavoidably remains at a bottom of one of the openings that is directed to the base contact region. This is because p-type impurity ions are injected through the field oxide film on forming the base contact region. Either by thermal oxdization or by injection of oxygen ions, the field oxide film is given a high or excessive oxygen content. It now becomes possible to completely remove the field oxide film by chemical etch, as by hydrofluoric acid, and to bring an electrode into execellent ohmic contact with the base contact region.
    Type: Grant
    Filed: February 22, 1993
    Date of Patent: December 13, 1994
    Assignee: NEC Corporation
    Inventor: Akio Matsuoka
  • Patent number: 5352636
    Abstract: A method is described for cleaning a silicon surface of a semiconductor wafer in a vacuum chamber while radiantly heating said silicon surface to maintain it within a first temperature range in the presence of hydrogen gas; then quickly cooling the wafer down to a second temperature range by reducing the radiant heat; and then forming a layer of either polysilicon or oxide over the cleaned surface within this second temperature range without removing the cleaned wafer from the chamber. By cleaning the wafer and then depositing polysilicon or growing oxide over the cleaned silicon surface in the same vacuum chamber, formation of oxides and other contaminants on the cleaned silicon surface between the cleaning step and the deposition or growth step is inhibited, resulting in a higher quality polysilicon or oxide layer formed over the cleaned silicon surface.
    Type: Grant
    Filed: January 16, 1992
    Date of Patent: October 4, 1994
    Assignee: Applied Materials, Inc.
    Inventor: Israel Beinglass
  • Patent number: 5348913
    Abstract: In a preferred embodiment of the invention, a substrate (11) is cleaned by immersing it in an organic solvent (17) and subjecting it to acoustic energy, immersing it in alcohol, immersing it in a surfactant, subjecting it to a cascading rinse in deionized water, baking it (FIG. 3 ), and thereafter subjecting it to ultraviolet light in an ozone ambient (FIG. 4). When the foregoing steps are followed, the contact angle is significantly reduced, and an encapsulant (14) that is thereafter applied provides more reliable protection to an encapsulated device (12) from outside contaminants.
    Type: Grant
    Filed: August 6, 1993
    Date of Patent: September 20, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Richard McBride, Ching-Ping Wong
  • Patent number: 5344793
    Abstract: An method of providing defect enhanced CoSi2 formation and improved silicided junctions in deep submicron MOSFETs. A silicon wafer having a diffusion window is first precleaned with hydrofluoric acid. After the HF precleaning, the silicon wafer is transferred to a conventional cobalt sputtering tool where it is sputter cleaned by bombardment with low energy Ar+ ions so as to form an ultra-shallow damage region. After the sputter cleaning, and without removing the wafer from the sputtering tool, Cobalt metal is deposited on the silicon wafer at room temperature and a CoSi2 layer is formed in the diffusion window.
    Type: Grant
    Filed: March 5, 1993
    Date of Patent: September 6, 1994
    Assignee: Siemens Aktiengesellschaft
    Inventors: Heinrich Zeininger, Christoph Zeller, Udo Schwalke, Uwe Doebler, Wilfried Haensch
  • Patent number: 5332692
    Abstract: A sputtering technique is conducted within a sputtering device the inside of which is in the state of vacuum, whereby a second polycrystal silicon film (7) is deposited on a first polycrystal silicon film (3) on the surface of which a natural oxide film (4) exists. The inside of the sputtering device is maintained to be in the state of vacuum after the second polycrystal silicon film (7) is formed. With the same sputtering device, a metal silicide film (5) is deposited on the second polycrystal film under vacuum. When a silicon oxide film is formed on the silicide film, silicons to be oxidized are uniformly supplied through the silicide film. Therefore, the polycrystal silicon film and the silicide film are not separated from each other at the boundary face between them. Further, product yield rate is improved since it is not necessary to perform sputter etching.
    Type: Grant
    Filed: April 19, 1993
    Date of Patent: July 26, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kenji Saitoh
  • Patent number: 5330577
    Abstract: A semiconductor fabrication apparatus for forming a film on a wafer by a CVD method provides for easy removal of the dust generated in a film-forming chamber without reducing the uptime/downtime ratio of the equipment. The apparatus includes one or more gas dispersing devices having gas releasing surfaces for releasing a reaction gas to form a film on a wafer; one or more wafer holders having wafer mounting surfaces opposed to the plane defined by the gas releasing surface; and one or more cleaners, each having a suction port and a brush connected to the suction port, provided opposing the gas releasing surface. Either the cleaner or the gas dispersing device is moved so that the brush contacts and traverses the gas releasing surface.
    Type: Grant
    Filed: October 27, 1992
    Date of Patent: July 19, 1994
    Assignees: Semiconductor Process Laboratory Co., Inc., Canon Sales Co., Inc., Alcan-Tech Co., Inc.
    Inventors: Kazuo Maeda, Kouichi Ohira, Mitsuo Hirose
  • Patent number: 5328558
    Abstract: An NF.sub.3 /H.sub.2 mixture as a feed gas for an etchant for etching an SiO.sub.2 film on an silicon wafer is used with a 1 : 160 NF.sub.3 /H.sub.2 mixed ratio. The mixture is made into plasma, and activated species of fluorine, hydrogen and nitrogen are supplied downstream to allow the species to be adsorbed in and on the SiO.sub.2 film. The NF.sub.3 /H.sub.2 mixed ratio of the mixture is so set as not to effect the etching of the SiO.sub.2 film under a chemical action. Then the adsorbed activated species are irradiated with Ar low energy ions so that the activated species are excited and etch the SiO.sub.2 film. During etching, the semiconductor wafer is maintained to about -100.degree. C. Less damage is caused to the silicon wafer and etching can be made in a high selection ratio.
    Type: Grant
    Filed: March 25, 1993
    Date of Patent: July 12, 1994
    Assignees: Tokyo Electron Limited, Yasuhiro Horiike
    Inventor: Kouhei Kawamura
  • Patent number: 5328867
    Abstract: A method of removing impurities from the surface of an integrated circuit and forming a uniform thin native oxide layer on the same surface of an integrated circuit is described. A hydrofluoric acid solution, followed by a rinse and spin dry, is often used to remove gate oxide from within an opening etched in a polysilicon layer. The rinsing leaves water spots. Spin drying leaves impurities where water tracks were. An H.sub.2 O.sub.2 cleaning is performed to remove the water spots. After the cleaning, a uniform thin layer of native oxide is formed on the surface of the silicon substrate. A second layer of polysilicon is deposited over this first thin native oxide layer and doped with an implant dosage chosen so that it will go through the uniform native oxide layer. The substrate is annealed to drive in the buried contact. Processing continues to form polysilicon or silicide gate electrodes. Source and drain regions are formed within the openings to the silicon substrate between the gate electrodes.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: July 12, 1994
    Assignee: United Microelectronics Corporation
    Inventors: Sun-Chieh Chien, Yu-Ju Liu
  • Patent number: 5312780
    Abstract: A method for forming an anti-reflective coating useful in the fabrication of integrated circuits is discussed. Applicants have found that preheating semiconductor wafers prior to the application of amorphous silicon anti-reflective coatings tends to reduce undesirable particulates which may attach to the wafer. The process is illustratively performed in a Varian 3180 machine having four stations. Illustratively, the wafer may be preheated between 70.degree. C. and 175.degree. C. prior to and during the sputter deposition of an amorphous silicon anti-reflective coating.
    Type: Grant
    Filed: December 16, 1992
    Date of Patent: May 17, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Arun K. Nanda, Mark J. Sundahl, Edward J. Vajda
  • Patent number: 5310711
    Abstract: Very shallow electrical junctions may be formed in an oxide free surface of a semiconductor by introducing an inert or reducing gas into a vacuum processing chamber, heating the semiconductor to between 750.degree. C. and 1100.degree. C., introducing a dilute solution of a dopant gas into the chamber, and exposing the semiconductor to the gases for about 0.5 to about 100 minutes, preferably between 10 and 30 minutes. A relatively wide range of surface dopant concentrations may be achieved thereby with dopant concentration controlled independent of junction depth. Non-oxide free semiconductor surfaces may be made oxide free by first heating the semiconductor surface in the presence of the reducing gas. This technique provides uniform surface dopant concentrations and is suitable for the formation of junctions in deep trenches and other features having high aspect ratios.
    Type: Grant
    Filed: August 2, 1993
    Date of Patent: May 10, 1994
    Assignee: Hewlett-Packard Company
    Inventors: Clifford I. Drowley, John E. Turner
  • Patent number: 5310697
    Abstract: A method for fabricating an AlGaInP semiconductor light emitting device having a substrate and a multilayer structure including an AlGaInP first semiconductor layer formed on the substrate. The method comprises the steps of removing part of the multilayer structure so that the first semiconductor layer is exposed, irradiating with plasma beams an oxide film formed on the exposed first semiconductor layer with the substrate temperature being kept at 500.degree. C. or less, so as to remove the oxide film from the first semiconductor layer and growing a second semiconductor layer on the first semiconductor layer.
    Type: Grant
    Filed: December 18, 1992
    Date of Patent: May 10, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuo Kan, Kosei Takahashi, Masahiro Hosoda, Atsuo Tsunoda, Kentaro Tani
  • Patent number: 5294572
    Abstract: Method and apparatus for the batchwise simultaneous treatment of several substrates by chemical vapor deposition. The method is carried out in a closed system and before the deposition treatment, the substrates are subjected to a cleaning treatment in the same system.
    Type: Grant
    Filed: November 1, 1991
    Date of Patent: March 15, 1994
    Assignee: ASM International N.V.
    Inventors: Ernst H. A. Granneman, Hans W. Piekaar, Hubertus A. Corsius, Boudewijn G. Sluijk
  • Patent number: 5294568
    Abstract: A method of selective etching of native oxide on a substrate is disclosed in which hydrogen halide vapor and water vapor are exposed to the substrate surface under appropriate conditions and long enough to remove native oxide but not long enough to remove any significant amount of other oxides. Treating conditions are maintained to prevent water vapor from condensing on the substrate until sufficient native oxide is etched so that substantially all the native oxide will be etched before appreciable other oxides are etched.
    Type: Grant
    Filed: April 10, 1992
    Date of Patent: March 15, 1994
    Assignee: Genus, Inc.
    Inventors: Michael A. McNeilly, Bruce E. Deal, Dah-Bin Kao, John de Larios
  • Patent number: 5275687
    Abstract: In accordance with the invention, a contaminated III-V semiconductor surface is cleaned by the sequential steps of exposure to hydrogen plasma, chemical etching in chlorine and annealing in vacuum. In a preferred embodiment, a semiconductor of the gallium arsenide family is subjected to hydrogen plasma in an ECR system for 20-120 minutes, then, without breaking vacuum, subjected to a Cl.sub.2 chemical etch at 250.degree. C.-450.degree. C. for 1-5 minutes. Again, without breaking vacuum, the semiconductor is annealed at 200.degree. C.-600.degree. C. for 5-15 minutes. To obtain good surface reconstruction, annealing preferably takes place at a temperature 300.degree. C. or above. The semiconductor surface thus processed is atomically smooth and sufficiently clean to permit regrowth of a high quality epitaxial layer.
    Type: Grant
    Filed: November 20, 1992
    Date of Patent: January 4, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Kent D. Choquette, Robert S. Freund, Minghwei Hong, Joseph P. Mannaerts
  • Patent number: 5244144
    Abstract: A method is provided to braze aluminum materials to each other, the method comprising a step of producing a fluoride gas-containing atmosphere within a brazing oven. The method further comprises a step of brazing the aluminum materials, by heating said materials within said atmosphere melts. The fluoride gas-containing atmosphere is produced in the soldering oven: by introducing an inert gas and the fluoride gas through different passages; by introducing into the oven a mixture of the inert gas and the fluoride gas; or by heating a fluoride in a receptacle which is placed in the oven so as to gasify the fluoride within the oven.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: September 14, 1993
    Assignee: Showa Aluminum Kabushiki Kaisha
    Inventors: Yasuhiro Osame, Satoko Arai, Shoichi Sato, Shuichi Murooka
  • Patent number: 5238871
    Abstract: A method of manufacturing a semiconductor device including a MOS-type field effect transistor includes cleansing a surface of a substrate; forming, next to the cleansing step, a gate oxide film on the cleansed surface of the substrate; wherein the cleansing step includes dry-etching the surface of the substrate in an atmosphere in which hydrogen fluoride and a substance containing at least a chlorine atom coexist in gaseous state and removing an oxide film and metal impurities on the surface of the substrate. Preferably, the dry-etching is performed under heat and decompression.
    Type: Grant
    Filed: November 25, 1991
    Date of Patent: August 24, 1993
    Assignee: Seiko Epson Corporation
    Inventor: Masato Sato
  • Patent number: 5238849
    Abstract: A bipolar transistor having a silicon oxide film having a stoichiometric composition ratio of silicon to oxygen controlled to 1 to 2 formed at the boundary between a monocrystalline layer and a polycrystalline layer. In fabrication, a natural oxidized film formed on the surface of an intrinsic base region of a single-crystal is removed in an ultrahigh-vacuum chamber. Subsequently, oxygen ions are supplied to the surface of the base region at room temperature to form a silicon oxide film. Further, silicon molecular beams are supplied in the same chamber to form the polycrystalline silicon layer. The current gain factor h.sub.FE of the bipolar transistor thus formed can be greatly improved.
    Type: Grant
    Filed: August 30, 1991
    Date of Patent: August 24, 1993
    Assignee: NEC Corporation
    Inventor: Fumihiko Sato
  • Patent number: 5238878
    Abstract: Upon the formation of a film on a semiconductor substrate by spin coating method, a polyimide precursor solution as a film forming solution is supplied dropwise onto the semiconductor substrate, and then the semiconductor substrate is started to be rotated at a low revolving speed of 1,000 rpm while pure water as an adhesion protecting liquid is injected upon the backside of the semiconductor substrate. By this operation, the polyimide precursor solution is spread out over the above surface of the semiconductor substrate by the rotation thereof. On the other hand, pure water is injected on the backside of the substrate before the dropped solution reaches the periphery of the substrate. As a result, the polyimide precursor liquid is prevented from going around to the backside of the substrate by the injection of pure water, thus protecting the adhesion of the polyimide precursor solution onto the backside of the substrate.
    Type: Grant
    Filed: February 18, 1993
    Date of Patent: August 24, 1993
    Assignee: NEC Corporation
    Inventor: Masahide Shinohara
  • Patent number: 5232872
    Abstract: A method of forming metal contact wiring layers in semiconductor devices by cleaning the surface of an exposed substrate of a contact hole formed to the SiO.sub.2 film on a semiconductor substrate with the reducing effect of N.sub.2 H.sub.4 gas, thereafter forming a TiN barrier layer by the CVD method using the mixed gas of N.sub.2 H.sub.4 and TiCl.sub.4 while the surface is not exposed to the air, then forming a tungsten contact layer thereon by the CVD method using the mixed gas of N.sub.2 H.sub.4 and WF.sub.6, or forming the TiN layer by the CVD method on the tungsten contact layer formed by the CVD method on the substrate.
    Type: Grant
    Filed: March 5, 1992
    Date of Patent: August 3, 1993
    Assignee: Fujitsu Limited
    Inventor: Takayuki Ohba
  • Patent number: 5198071
    Abstract: A process for the formation of an epitaxial layer on a semiconductor wafer is described which inhibits the formation of thermal stress in the semiconductor wafer such as a silicon wafer, during the formation of such an epitaxial layer thereon. In one aspect, such thermal stress is inhibited during the deposition of the epitaxial material by initially reducing the deposition rate to less than 1 .mu.m per minute or lower until the epitaxial layer reaches a thickness of from about 2 to about 30 .mu.m. In another aspect of the invention, any bridge materials formed between the wafer and the wafer support, during formation of the epitaxial layer, is removed before the wafer is cooled, i.e., before such bridge materials can induce thermal stress in the wafer during the cooling of the wafer, by post etching the wafer with HCl etching gas after the epitaxial deposition.
    Type: Grant
    Filed: November 25, 1991
    Date of Patent: March 30, 1993
    Assignee: Applied Materials, Inc.
    Inventors: Lance Scudder, Norma Riley
  • Patent number: 5196375
    Abstract: A method for manufacturing a bonded semiconductor body including contacting the flat mirror surfaces of semiconductor substrate wafers used as semiconductor element substrates, and subjecting the adhered semiconductor substrate wafers to a heat treatment at a temperature higher than 200.degree. C. and lower than the melting point of the semiconductor substrate wafers to bond the mirror surfaces. The surface roughness of each of the mirror surfaces of the semiconductor substrate wafers is set not more than 130 .ANG. at its maximum value when measured in a range of 1 mm on a reference plane provided in a predetermined area of the mirror surface.
    Type: Grant
    Filed: July 29, 1991
    Date of Patent: March 23, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadahide Hoshi
  • Patent number: 5194397
    Abstract: A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.
    Type: Grant
    Filed: June 5, 1991
    Date of Patent: March 16, 1993
    Assignee: International Business Machines Corporation
    Inventors: Robert K. Cook, Ronald W. Knepper, Subodh K. Kulkarni, Russell C. Lange, Paul A. Ronsheim, Seshadri Subbanna, Manu J. Tejwani, Bob H. Yun
  • Patent number: 5188987
    Abstract: A method of manufacturing a semiconductor device comprises the steps of performimg selective vapor growth on a semiconductor substrate, and polishing a surface of an insulative film formed on said semiconductor substrate subsequent to the selective vapor growth step.
    Type: Grant
    Filed: June 12, 1991
    Date of Patent: February 23, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masanobu Ogino
  • Patent number: 5151135
    Abstract: The invention relates to a new method for cleaning chemical, metallic and particulate contaminants from solid surfaces. The new method comprises irradiating the surface with essentially ultraviolet laser radiation whose parameters are selected to avoid causing substantial chemical or physical change at the surface.
    Type: Grant
    Filed: September 15, 1989
    Date of Patent: September 29, 1992
    Assignee: Amoco Corporation
    Inventors: Thomas J. Magee, Charles S. Leung, Richard L. Press
  • Patent number: 5122482
    Abstract: In a method for treating the surface of either crystalline or amorphous silicon a silicon material is maintained in a non-oxidizing atmosphere with a reduced pressure, a gas selected from among hydrides of phosphorus, fluorides of phosphorus, hydrides of arsenic, fluorides of arsenic, hydrides of boron, fluorides of boron and fluorides of silicon is excited and the excited gas is supplied onto the surface of the silicon material for a prescribed period of time. During this period the temperature of the silicon material is maintained within a range higher than the temperature at which the molecules of the selected gas would, were the gas not excited, liquefy at the reduced pressure and deposit on the material and lower than the temperature at which the gas decomposes. The method enables the silicon material surface to be cleaned and/or protected by treatment at a relatively low temperature.
    Type: Grant
    Filed: March 23, 1990
    Date of Patent: June 16, 1992
    Assignees: Agency of Industrial Science & Technology, Ministry of International Trade & Industry
    Inventors: Yutaka Hayashi, Yasushi Kondo
  • Patent number: 5120394
    Abstract: A process of epitaxially growing a semiconductor Si, Ge or SiGe single crystal layer on a semiconductor (Si or Ge) single crystal substrate, comprising the steps of: allowing a raw material gas (e.g., Si.sub.2 H.sub.6, GeH.sub.4) for the layer and a fluoride gas (e.g., Si.sub.2 F.sub.6, GeF.sub.4, BF) of at least one element selected from the group consisting of the semiconductor element of the layer and a dopant for the layer to simultaneously flow over the substrate; and applying an ultraviolet light to the substrate to decompose the gases by an ultraviolet light excitation reaction to deposit the layer on the surface of the substrate heated at a temperature of from 250.degree. to 400.degree. C.Prior to the epitaxial growth of the semiconductor layer, the substrate is cleaned by allowing the fluoride gas to flow over the substrate having a temperature of from a room temperature to 500.degree. C.
    Type: Grant
    Filed: November 9, 1989
    Date of Patent: June 9, 1992
    Assignee: Fujitsu Limited
    Inventor: Ryoichi Mukai
  • Patent number: 5100839
    Abstract: A rod base material for forming wafers for electronic devices is formed from a plurality of rod members made of selected materials. The rods are assembled in parallel and are bonded with each other into an integrated body. In one aspect of this invention, a mirror-finished bonding face is formed at the outer surface of each of the rod members, and is cleaned by a surface treatment using chemicals. Subsequently, respective rod members are assembled in parallel and brought into contact with each other at their respective bonding faces. The thus prepared and assembled rod members are maintained in a heated atmosphere until they combine into an integrated body to provide the base material. The rod base material is thereafter subjected to slicing to provide wafers used for forming electronic devices.
    Type: Grant
    Filed: January 31, 1991
    Date of Patent: March 31, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Noboru Terao
  • Patent number: 5089441
    Abstract: A low-temperature (650.degree. C. to 800.degree. C.) in-situ dry cleaning process (FIG. 2) for removing native oxide (and other contaminants) from a semiconductor surface can be used with either multi-wafer or single-wafer semiconductor device manufacturing reactors. A wafer is contacted with a dry cleaning mixture of germane GeH.sub.4 and hydrogen gas (51), such that the germane:hydrogen flow ratio is less than about 0.15:12000 sccm. The dry cleaning mixture can include a halogen-containing gas (such as HCl or HBr) (52, 54) to enhance cleaning of metallic contaminants, and/or anhydrous HF gas (53, 54) to further lower the process temperature. The dry cleaning process can be achieved by introducing some or all of the hydrogen and/or an inert gas as a remote plasma. The dry cleaning process is adaptable as a precleaning step for multiprocessing methodologies that, during transitions between process steps, reduce thermal cycling (FIGS. 3c-3e) by reducing wafer temperature only to an idle temperature (350.
    Type: Grant
    Filed: April 16, 1990
    Date of Patent: February 18, 1992
    Assignee: Texas Instruments Incorporated
    Inventor: Mehrdad M. Moslehi
  • Patent number: 5087590
    Abstract: With a method of and an apparatus for manufacturing semiconductor devices using copper-type lead frames with no silver plating, semiconductor devices are continuously manufactured in the following steps: first, a semiconductor pellet having electrodes on its surface is bonded, through a resin material, to a die pad on a copper-alloy lead frame which is not silver-plated. The resin material used for the bonding is then cured by heating it for 120 seconds or less in a non-oxidizing-gas atmosphere having an oxygen density of 1000 ppm or less. Then, the thickness of the oxide film which is formed on the surface of the lead frame while curing the resin material is reduced to 20 .ANG. or less by keeping the lead frame in a deoxidizing-gas atmosphere having an oxygen density of 500 ppm or less.
    Type: Grant
    Filed: October 24, 1989
    Date of Patent: February 11, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hitoshi Fujimoto, Hisao Masuda, Shuichi Osaka, Noriaki Uwagawa
  • Patent number: 5078801
    Abstract: A method for cleaning the surface of an oxidized semiconductor wafer subjected to a planarization polishing process is described. The planarization process employes a slurry which contains abrasive particles suspended in a liquid solution. The invented cleaning method removes remnant particles electrochemically by placing the polished wafers in a PH-controlled bath.
    Type: Grant
    Filed: August 14, 1990
    Date of Patent: January 7, 1992
    Assignee: Intel Corporation
    Inventor: Farid A. Malik
  • Patent number: 5037774
    Abstract: Process for the production of semiconductor devices by using silicon-on-insulator (SOI) techniques. The Si layers of the SOI structure include an interfacial layer of Si and a buffer layer of Si formed thereon, whereby the formation of stacking faults in the Si layers can be effectively prevented. Pretreatment of the underlying insulating material with a molybdate solution and interposition of an additional layer of slowly grown single-crystalline Si between the buffer layer of Si and the overlying active Si layer are also effective to inhibit the stacking faults. Semiconductor devices with high quality can be produced with good yield.
    Type: Grant
    Filed: July 15, 1987
    Date of Patent: August 6, 1991
    Assignee: Fujitsu Limited
    Inventors: Hideki Yamawaki, Yoshihiro Arimoto, Shigeo Kodama, Takafumi Kimura, Masaru Ihara
  • Patent number: 5028560
    Abstract: A method and apparatus for manufacturing a semiconductor device having a thin layer of material formed on a semiconductor substrate with a much improved interface between them are disclosed. A silicon substrate is heated up to a temperature around 300.degree. C. in the presence of ozone gas under exposure to UV light. Through this process, organic contaminants that might be present on the surface of the silicon substrate are dissipated by oxidation, and a thin oxide film is formed on the substrate surface on the other. The silicon substrate with the thin oxide film coated thereon is then heated up to temperature of 200.degree.-700.degree. C. in the presence of HCl gas under illumination to UV light to strip the oxide film off the substrate surface, thereby exposing the cleaned substrate surface. Finally, HCl cleaned surface of the silicon substrate is coated with a thin layer of material such as monocrystalline silicon without exposing the cleaned substrate surface.
    Type: Grant
    Filed: March 1, 1989
    Date of Patent: July 2, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuhiro Tsukamoto, Akira Tokui
  • Patent number: 5024968
    Abstract: A method and apparatus for removing surface contaminants from the surface of a substrate by high-energy irradiation is provided. The invention enables removal of surface contaminants without altering of the substrate's underlying molecular structure. The source of high-energy irradiation may comprise a pulsed laser.
    Type: Grant
    Filed: July 8, 1988
    Date of Patent: June 18, 1991
    Inventor: Audrey C. Engelsberg